IBM Unveils World's First Sub-Nanometer Chip Architecture

IBM has revealed a new transistor architecture called nanostack, designed for the 0.7-nanometer node and capable of packing nearly 100 billion transistors onto a fingernail-sized chip. The technology promises 50% better performance and 70% greater energy efficiency compared to IBM's two-nanometer chips, with significant SRAM improvements relevant to AI workloads. Nanostack builds on existing nanosheet technology by adding vertical transistor stacking, enabling chip scaling to continue below 1nm. IBM says the technology is still on a research-to-manufacturing path, with commercial adoption expected within five years.